This application claims the priority of Korean Patent Application No. 2004-66168, filed on Aug. 21, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a digital signal processing, and more particularly, to hardware having a systolic array structure for separating multiple input blind source signals.
2. Description of Related Art
As electronics is advanced, a variety of techniques for processing digital signals in high speed have been developed. At this time, information digitalization is being progressed to meet the future needs for a multimedia era, and, accordingly, information processing technologies have been continuously developed according to corresponding application fields.
The remarkable development in the digital signal processing allows a digital image/video communication to be widely commercialized so that technologies for processing multimedia and moving pictures are being particularly developed. Unfortunately, since a huge amount of data must be processed to handle image signals, many constraints still exist to efficiently transmit or store the digital image information. Recently, there have been tendencies to integrate Internet, multimedia, and information communication, and, accordingly, the image communication fields are also being integrated and standardized. Also, mixed services of videos, voices, additional information, as well as high quality multimedia are being commercialized.
Meanwhile, many of the image processing techniques are based on a motion compensation inter-frame discrete cosine transform (DCT) algorithm. In the DCT algorithm, image data are converted into coefficient data in a frequency domain, and their energies are concentrated on a low frequency band to convert them to an easily compressible form, so that compression efficiency of a corresponding application system can be significantly improved. Therefore, the DCT algorithm is widely applicable to many kinds of systems requiring data compression such as a high definition television (HDTV). In addition, the size of the image processing apparatus can be minimized, so that miniaturization of application products can be also facilitated.
Subsequently, a variety of techniques have been developed to implement the digital data processing methods such as the DCT algorithm. Such techniques include a distributed arithmetic method, and other methods of using ROMs, typical multipliers, and the like. According to the method of using typical multipliers, a fast algorithm is derived based on a 2-dimensional DCT/IDCT equation. To increase data processing speed in the method of using multipliers, it is important to reduce the number of necessary multiplications or increase the number of concurrent operations.
FIG. 1 is a schematic block diagram for describing a parallel data processing inside hardware.
Since a plurality of processing elements PE1, PE2, . . . , PEn are concurrently operated, processing speed can be increased in comparison with the method in which they are individually operated. Accordingly, the parallel data processing shown in FIG. 1 can be used to increase digital signal processing speed.
The method of using multipliers can be classified into a butterfly structure type and a systolic array structure type. In the butterfly structure, since data must be transmitted to an entire circuit, computation time is long, and the size of the circuit is also large. On the other hand, in the systolic array structure, processing speed of a particular algorithm can be increased by using a parallel processing, and ASIC type hardware is usually employed. Features of the systolic array structure are modularity, regularity, local connectivity, and synchrony.
FIG. 2 is a schematic block diagram illustrating a systolic structure type data processing technique.
As recognized in FIG. 2, input data are processed with interconnectivity. The systolic method has been developed to meet needs in a particular application field such as a signal processing or an image processing, and shows excellent performance and cost-efficiency. In addition, the systolic structure has regularity in a data flow and a control flow, and its components are connected in parallel, so that the control flow and the data flow are iterated in the same path. Accordingly, it is said that the systolic structure is designed to combining features of a pipeline vector processor and an array processor.
Such a systolic structure can be applied to, for example, a blind source separation algorithm for separating blind source signals from the input mixture.
To accommodate a speech recognition system, it is necessary to separate a particular user's voice from other user's voices or background noises. This is because the speech recognition system shows excellent performance during the test in an anechoic room, but its recognition rate is significantly reduced in a real life environment due to noises. The recognition rate of the speech recognition system can be improved by using such a blind source separation method. Furthermore, time consumption for such unnecessary noises can be reduced. Substantial studies for such a blind source separation have been initiated from early 1990's.
However, existing studies on the voice recognition system have been focused on a theoretical investigation on algorithms. Therefore, while software capable of implementing such algorithms has been widely known in the art, hardware implementing them on a chip has been poorly investigated. Needless to say, it is necessary to implement the voice recognition system in hardware in order to accommodate it in our everyday life.
For this reason, there is a need in the art for an apparatus for separating blind source signals that is implemented in hardware.